Semiconductor Engineering

Hardware-Accelerated RTL Simulator

A technical paper titled “Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism” was published by researchers at EPFL, University of Tokyo, Sharif University, and ...
Electronic Design

How to Become an RTL Simulation Expert vs. Hardware Emulation Expert

In Part 1, we reviewed the process of designing a modern hardware emulation platform. Here, we’ll look at the skills and training that are necessary to become a simulation expert and an emulation ...
Business Wire

Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM™ simulation ...
Design-Reuse

Embedded Linux Co-simulation

The augmentation of number of gates on chip makes SOC design more difficult. So we have to work on SOC design tools to make designer work easier and manage all the available gates. We propose an ...
T&D

Transforming the grid with real-time simulation and hardware-in-the-loop

Real-time power system simulation and hardware-in-the-loop (HIL) testing have been transforming the power industry for over 30 years. These tools have revolutionized the way that engineers study power ...
Design-Reuse

Reusable Device Simulation Models for Embedded System Virtual Platforms

As embedded systems hardware is becoming more powerful, the demand for high quality, sophisticated and compelling applications is increasing. In addition to that, due to fierce competition in the ...